The invention pertains to semiconductor fabrication. More particularly, the invention pertains to improving performance of semiconductor devices by stress engineering.
In the fabrication of semiconductor devices, there is a constant drive to make the devices smaller and more densely packed. However, there are limits to these reductions due to performance and fabrication issues. Accordingly, attention has been given to ways to increase the performance of semiconductor circuits.
One such solution involves selectively orienting the crystal lattice structure of the semiconductor substrate to improve device performance. Particularly, the orientation of the crystal lattice of the material results in different electron and/or hole mobility, and thus different performance of the semiconductor devices. For instance, substrates having a 1-0-0 crystal lattice orientation favor electron mobility and are thus preferred for nFET devices, whereas substrates having a 1-1-0 crystal lattice orientation provide good hole mobility and are thus preferred for pFET devices. Accordingly, techniques have been developed to create semiconductor substrates that have different regions with different crystal lattice orientations. The n-type devices are fabricated in the regions having 1-0-0 orientation while the p-type devices are fabricated in the regions having 1-1-0 orientation. These techniques are often referred to as hybrid orientation techniques. In one type of hybrid orientation process, two layers of crystallized and oriented semiconductor substrates are directly bonded to each other, one layer crystallized in the 1-1-0 orientation and the other layer crystallized in the 1-0-0 orientation and the lower, e.g., 1-1-0 -oriented, layer brought to the top surface of the substrate in selected regions.
There are several techniques known for accomplishing this task. In one technique, the top layer is etched completely through (i.e., removed) in selected regions so as to expose the underlying layer. The exposed lower layer material is epitaxially grown to bring it up to the same height as the top surface of the remaining 1-0-0 oriented material. Alternately, the upper layer material is amorphized in selected regions by depositing ions. Then, the wafer is annealed to recrystallize the upper layer in the selected regions, the material recrystallizing to the orientation of the 1-1-0 orientation of the material layer underneath it. Another solution involves applying mechanical stress to the crystal lattice structure of the semiconductor material so as to distort the crystal lattice of the material, which increases the electron and/or hole mobility in the material.
In one technique for adding mechanical stress to a semiconductor substrate after the devices have been created in the substrate, a stress liner, such as a nitride layer, is deposited on top of the substrate. The direction and amount of stress is controllable by the particular process parameters used to deposit the stress liner, such as the thickness of the stress liner (which primarily affects the amount of stress), the temperature and pressure of the vapor process, and the impurities (e.g., materials in addition to nitride) intentionally included in the layer. In another technique known as stress memory transfer, previously crystallized semiconductor material is amorphized and then an external mechanical stress is applied to the substrate, such as by depositing a nitride stress liner on top of the substrate. Next, the amorphized material is recrystallized, such as by annealing, while the substrate is subject to the external stress. Finally, the external mechanical stress is removed, such as by removing the nitride stress liner, and the stress, or at least much of it, remains baked into the substrate.